I am getting 40 MHz output at y4 how default value of io_00_34_ad9361_clksel is high? How to configure ad9361 clkout?
Not sure what you are doing, but the answer to 'how to control the clock-out" is here:
Just note the clock out is a function of the adc-clk & mainly for sync.
As for the second part, I doubt your question is really about "what is the purpose of different folders" (that will be obvious) -- anyway someone here will answer.
What board are you using?
Hello I have picozed sdr kit. I have downloaded ad9361 driver files from github. Pls let me know how can I use them to configure clock?
Are you using the FMC carrier along with the ADRV9361-Z7035?
What are you configuring the clock to? The board should already be working.
Can you please be a little bit more specific as to what your end goal is?
yes i have a mother board. i am trying t implement no-os design. i have downloaded files from github. i want to give a clock to processor in fpga.
What is the purpose of different folders in ad9361 driver ? Console_commands, platform _generic, platform _xilinx, platform _linux?
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