This is for one of our customers.
They encountered an issue with the amplitude of the data clock, it is very low, only around 800mv pk-pk. and not as expected from a driving side.
Datasheet have it as Vdd i/f * 0.8. As Vdd i/f is 2.5V, this should be ~2.0V.
They are working at burst mode and the clock is approximately 22.5Mhz.
When they are driving 11.2Mhz data clock the amplitude of the signal is twice as with the higher freq, (~1.6V) All this is done on the same platform!!
When they tries to increase the drive strength of the AD9361(+20%) the improvement was noticed but not enough to meet the receiver thresholds which are LVCMOS33 std.
I’m attaching two scope captures that shows this issue.