AnsweredAssumed Answered

How to change output clock  channel-divider value for ad9528 in ADRF9371 Eval Board?

Question asked by amdakwar12 on Aug 4, 2017
Latest reply on Aug 9, 2017 by amdakwar12

I am using zc706 + adrf9371 Eval board for testing.


I am using SD card images R2016_2 version relase on 29-06-2017 dated.


Now I wish to change output clock from channel 1of AD9528 to 245.76 MHz , for that I had made change in device tree for ad9528  as follows

                   channel@1 {
                    reg = <0x1>;
                    adi,extended-name = "FMC_CLK";
                    adi,driver-mode = <0x0>;
                    adi,divider-phase = <0x0>;
                    adi,channel-divider = <0x5>;                 /* Initially this value was 0xa for 122.88 MHz clock  */
                    adi,signal-source = <0x0>;



But I am unable to see any changes in output clock.


Always divider value is showing is 0xa only.


Please suggest, how to change channel divider value?