We are using the 9371 board and are trying to configure a 2TX, 2RX lane system (no observation required). We can get the default 4TX and 2RX going using the NO-OS code.
We noticed that the FPGA JESD IP is hard coded to 4 lanes. Can we reconfigure this using software? If so, what steps are required to do this?
We have tried hard coding the FPGA JESD IP to use only 2 lanes, is this the correct method? This method did not work for us, we may be missing a configuration step.
We have changed the 9371.c file to reflect the use of only 2 deframer lanes. Does the crossbar need to be changed? Are there other parameters that need to change in the Mykonos in order to use only 2 TX lanes?
Any help on the matter would be greatly appreciated.