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AXI DMAC Streaming to MM-AXI No-OS Missing Byte

Question asked by jsusong on Aug 2, 2017
Latest reply on Aug 8, 2017 by rejeesh

I am using the Analog devices AXI_DMAC IP (see link below) block in a Xilinx Zynq+ design and noticing the last byte of the DMA transaction is not getting transferred when using the No-OS driver.  I have tried increasing the length of the DMA transfer by one and this resolves the problem, however, it causes the subsequent AXI Bus transfer to write twice to the next memory location which causes data to be lost.  Is this a known issue with the AXI_DMAC IP?  If so, is there a workaround solution?




No-OS Source


Attached is a screenshot that shows how the DMAC is configured in my application.  Also Attached are screenshots of the AXI bus transactions for both cases (no change to the driver and increasing the length by 1). 


  • Notice xstrb  is 7F during the last write to memory. Ref. No Changes to Bare Metal Driver.png
  • Notice the double write to memory address 0x01800200 in the “Increasing length by 1 Zoomed in.png” image.