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AD9361 data_clk always has phase noise

Question asked by 西门吹猫 on Aug 1, 2017
Latest reply on Aug 4, 2017 by sripad

We used the AD9361 TX test, found DATA_CLK there is a relatively large phase noise.
The interface level uses the CMOS mode, the interface rate is SDR, the port mode is DUAL PORT, and the sampling rate is set to 40MHz.
The calibration process has been passed, but the test found that the data sampling problems, resulting in the transmission baseband data error. The last volume under the DATA_CLK found a relatively large phase noise, the oscilloscope to capture the picture as follows:

Then debug the problem and find that the output 40MHz clock is stable without DC and TX quadrature calibration, as shown below. But if the calibration is done all the above problems will occur (calibration process is completed, the final state of the calibration state machine is calibration Done).

In addition there is a phenomenon: After calibration, the use of PIN MODE control ENSM state machine, TXNRX high, ENABLE pulled high, ENSM can not jump to TX state, has maintained the ALERT state (I do not know whether this phenomenon and DATA_CLK instability is related ).
Would like to ask what the problem is caused, how to solve?

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