I have decided to do a build of your HDL IP using supplied scripts, using make, as a reference. Much information is contained in the scripts, and I don't wish to carelessly omit any of it. Our design requires AXI4 stream interfaces in place of the DMA, these will be made external to the axi_ad9361 IP in order to simplify its upgradeability. Herein, however, lies the problem of tool compatibility.
I am using a ZC706 EVB for development. This is officially locked by Xilinx to version 2015.4. The nearest version of AD9361 HDL code I can find requires 2015.2, but a substantial number of changes have been made since then. Notably CMOS support, which might be needed in our final design. Even more notably, support for 1R1T mode, as used in our target device, the AD9364.
I would like to understand the policy behind requiring a Vivado version update. Clearly, many of the changes constitute on-going development and are written in innocuous code. Are any of the changes positively identified as critical? Or is it simply the case they have not been tested on earlier versions of the the tool? I am more-or-less compelled to disable version checking, otherwise I will need to implement serious modifications, which, in themselves, carry risk, simply to be able to support the 9364.
Xilinx are unwilling to allow the ZC706 to be used with more recent versions than 2015.4, and, given the quite counter-intuitively entangled, quantum-mechanical predictability of their user interface, I sympathise. Your code, on the other hand, gives the impression of being fairly solid. I would therefore find it very useful to know if there have been important revisions to any of the Xilinx primitives you use in the design since 2015.2, which might might be misinterpreted by the earlier tool and adversely affect the operation of the AD9364. I/O and multipliers, I think, cover it.