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Assistance on IP-CORE ADI AXI DMA Controller (1.0)

Question asked by lucaalfredo on Aug 1, 2017
Latest reply on Aug 4, 2017 by larsc


We want produce an FPGA project to obtain the continuous fft result real time from the radio receiver AD9364.

We have start from the analog device project HDL (particular version 2016 r2) from GitHub. On this system example, the samples resulting from the radio receiver, passing through on the IP-CORE type “ADI AXI DMA Controller (1.0)” named “axi_ad9361_adc_dma_0”.

This kind of component must be programmed with a “C” program (like no-OS from GitHub) running on micro. Some register must be set to identify:

-    the number of samples that can be output (AXI_DMAC_REG_X_LENGTH)

-    the start action (AXI_DMAC_REG_START_TRANSFER)

On my final target project is necessary have a continuous sample flow.

Is it possible?

Documentation on “IP-CORE ADI AXI DMA Controller (1.0)” is not exhaustive, the settings of registers to obtain my goal is not clear.

Other question, is possible to set the  “IP-CORE ADI AXI DMA Controller (1.0)” only from FPGA? My final target is to create a project with only FPGA component without “C” program on micro.



  1. Can the “IP-CORE ADI AXI DMA Controller (1.0)” be programmed to obtain continuous samples flow?
  2. Can be use only FPGA to set the “IP-CORE ADI AXI DMA Controller (1.0)” registers?