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AD9467 FMC port to ZC706

Question asked by goli12 on Aug 1, 2017
Latest reply on Nov 17, 2017 by ccruztorre

Hi everyone

I have bought an AD9467 FMC to be interfaced through a ZC706. I have used the reference zedboard HDL project on the 2017_r1 branch as the backbone and removed components that do not interfere with the ADC functionality. Below is the board design in Vivado 2017.1.

 

board design

 

I was able to generate a bitstream and export it to the SDK. The problem occurs during adc_setup(0) and the following for loop within main.c. It looks like that when adc_delay_1 is called in adc_setup(0), the read rdata value is not equal to the delay value. A similar event also occurs during adc_test, where the rdata does not equal to edata. Below is the UART output which contains errors. I have added a few comments for debugging purposes.


********************************************************************
ADI AD9467-FMC-EBZ Reference Design
AD9467 CHIP ID: 0x50
AD9467 CHIP GRADE: 0x20
AD9517 CHIP ID: 0xD3
********************************************************************
AD9467[0x016]: 80
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
AD9467[0x016]: 80
AD9467[0x016]: 80
pcore_version: 10
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0001)
adc_delay_1: sel(10), rcv(0000), exp(0001)
adc_delay_1: sel(11), rcv(0000), exp(0001)
adc_delay_1: sel(12), rcv(0000), exp(0001)
adc_delay_1: sel(13), rcv(0000), exp(0001)
adc_delay_1: sel(14), rcv(0000), exp(0001)
adc_delay_1: sel(15), rcv(0000), exp(0001)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0002)
adc_delay_1: sel(10), rcv(0000), exp(0002)
adc_delay_1: sel(11), rcv(0000), exp(0002)
adc_delay_1: sel(12), rcv(0000), exp(0002)
adc_delay_1: sel(13), rcv(0000), exp(0002)
adc_delay_1: sel(14), rcv(0000), exp(0002)
adc_delay_1: sel(15), rcv(0000), exp(0002)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0003)
adc_delay_1: sel(10), rcv(0000), exp(0003)
adc_delay_1: sel(11), rcv(0000), exp(0003)
adc_delay_1: sel(12), rcv(0000), exp(0003)
adc_delay_1: sel(13), rcv(0000), exp(0003)
adc_delay_1: sel(14), rcv(0000), exp(0003)
adc_delay_1: sel(15), rcv(0000), exp(0003)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0004)
adc_delay_1: sel(10), rcv(0000), exp(0004)
adc_delay_1: sel(11), rcv(0000), exp(0004)
adc_delay_1: sel(12), rcv(0000), exp(0004)
adc_delay_1: sel(13), rcv(0000), exp(0004)
adc_delay_1: sel(14), rcv(0000), exp(0004)
adc_delay_1: sel(15), rcv(0000), exp(0004)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0005)
adc_delay_1: sel(10), rcv(0000), exp(0005)
adc_delay_1: sel(11), rcv(0000), exp(0005)
adc_delay_1: sel(12), rcv(0000), exp(0005)
adc_delay_1: sel(13), rcv(0000), exp(0005)
adc_delay_1: sel(14), rcv(0000), exp(0005)
adc_delay_1: sel(15), rcv(0000), exp(0005)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0006)
adc_delay_1: sel(10), rcv(0000), exp(0006)
adc_delay_1: sel(11), rcv(0000), exp(0006)
adc_delay_1: sel(12), rcv(0000), exp(0006)
adc_delay_1: sel(13), rcv(0000), exp(0006)
adc_delay_1: sel(14), rcv(0000), exp(0006)
adc_delay_1: sel(15), rcv(0000), exp(0006)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0007)
adc_delay_1: sel(10), rcv(0000), exp(0007)
adc_delay_1: sel(11), rcv(0000), exp(0007)
adc_delay_1: sel(12), rcv(0000), exp(0007)
adc_delay_1: sel(13), rcv(0000), exp(0007)
adc_delay_1: sel(14), rcv(0000), exp(0007)
adc_delay_1: sel(15), rcv(0000), exp(0007)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0008)
adc_delay_1: sel(10), rcv(0000), exp(0008)
adc_delay_1: sel(11), rcv(0000), exp(0008)
adc_delay_1: sel(12), rcv(0000), exp(0008)
adc_delay_1: sel(13), rcv(0000), exp(0008)
adc_delay_1: sel(14), rcv(0000), exp(0008)
adc_delay_1: sel(15), rcv(0000), exp(0008)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0009)
adc_delay_1: sel(10), rcv(0000), exp(0009)
adc_delay_1: sel(11), rcv(0000), exp(0009)
adc_delay_1: sel(12), rcv(0000), exp(0009)
adc_delay_1: sel(13), rcv(0000), exp(0009)
adc_delay_1: sel(14), rcv(0000), exp(0009)
adc_delay_1: sel(15), rcv(0000), exp(0009)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(000A)
adc_delay_1: sel(10), rcv(0000), exp(000A)
adc_delay_1: sel(11), rcv(0000), exp(000A)
adc_delay_1: sel(12), rcv(0000), exp(000A)
adc_delay_1: sel(13), rcv(0000), exp(000A)
adc_delay_1: sel(14), rcv(0000), exp(000A)
adc_delay_1: sel(15), rcv(0000), exp(000A)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(000B)
adc_delay_1: sel(10), rcv(0000), exp(000B)
adc_delay_1: sel(11), rcv(0000), exp(000B)
adc_delay_1: sel(12), rcv(0000), exp(000B)
adc_delay_1: sel(13), rcv(0000), exp(000B)
adc_delay_1: sel(14), rcv(0000), exp(000B)
adc_delay_1: sel(15), rcv(0000), exp(000B)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(000C)
adc_delay_1: sel(10), rcv(0000), exp(000C)
adc_delay_1: sel(11), rcv(0000), exp(000C)
adc_delay_1: sel(12), rcv(0000), exp(000C)
adc_delay_1: sel(13), rcv(0000), exp(000C)
adc_delay_1: sel(14), rcv(0000), exp(000C)
adc_delay_1: sel(15), rcv(0000), exp(000C)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(000D)
adc_delay_1: sel(10), rcv(0000), exp(000D)
adc_delay_1: sel(11), rcv(0000), exp(000D)
adc_delay_1: sel(12), rcv(0000), exp(000D)
adc_delay_1: sel(13), rcv(0000), exp(000D)
adc_delay_1: sel(14), rcv(0000), exp(000D)
adc_delay_1: sel(15), rcv(0000), exp(000D)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(000E)
adc_delay_1: sel(10), rcv(0000), exp(000E)
adc_delay_1: sel(11), rcv(0000), exp(000E)
adc_delay_1: sel(12), rcv(0000), exp(000E)
adc_delay_1: sel(13), rcv(0000), exp(000E)
adc_delay_1: sel(14), rcv(0000), exp(000E)
adc_delay_1: sel(15), rcv(0000), exp(000E)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(000F)
adc_delay_1: sel(10), rcv(0000), exp(000F)
adc_delay_1: sel(11), rcv(0000), exp(000F)
adc_delay_1: sel(12), rcv(0000), exp(000F)
adc_delay_1: sel(13), rcv(0000), exp(000F)
adc_delay_1: sel(14), rcv(0000), exp(000F)
adc_delay_1: sel(15), rcv(0000), exp(000F)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0010)
adc_delay_1: sel(10), rcv(0000), exp(0010)
adc_delay_1: sel(11), rcv(0000), exp(0010)
adc_delay_1: sel(12), rcv(0000), exp(0010)
adc_delay_1: sel(13), rcv(0000), exp(0010)
adc_delay_1: sel(14), rcv(0000), exp(0010)
adc_delay_1: sel(15), rcv(0000), exp(0010)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0011)
adc_delay_1: sel(10), rcv(0000), exp(0011)
adc_delay_1: sel(11), rcv(0000), exp(0011)
adc_delay_1: sel(12), rcv(0000), exp(0011)
adc_delay_1: sel(13), rcv(0000), exp(0011)
adc_delay_1: sel(14), rcv(0000), exp(0011)
adc_delay_1: sel(15), rcv(0000), exp(0011)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0012)
adc_delay_1: sel(10), rcv(0000), exp(0012)
adc_delay_1: sel(11), rcv(0000), exp(0012)
adc_delay_1: sel(12), rcv(0000), exp(0012)
adc_delay_1: sel(13), rcv(0000), exp(0012)
adc_delay_1: sel(14), rcv(0000), exp(0012)
adc_delay_1: sel(15), rcv(0000), exp(0012)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0013)
adc_delay_1: sel(10), rcv(0000), exp(0013)
adc_delay_1: sel(11), rcv(0000), exp(0013)
adc_delay_1: sel(12), rcv(0000), exp(0013)
adc_delay_1: sel(13), rcv(0000), exp(0013)
adc_delay_1: sel(14), rcv(0000), exp(0013)
adc_delay_1: sel(15), rcv(0000), exp(0013)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0014)
adc_delay_1: sel(10), rcv(0000), exp(0014)
adc_delay_1: sel(11), rcv(0000), exp(0014)
adc_delay_1: sel(12), rcv(0000), exp(0014)
adc_delay_1: sel(13), rcv(0000), exp(0014)
adc_delay_1: sel(14), rcv(0000), exp(0014)
adc_delay_1: sel(15), rcv(0000), exp(0014)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0015)
adc_delay_1: sel(10), rcv(0000), exp(0015)
adc_delay_1: sel(11), rcv(0000), exp(0015)
adc_delay_1: sel(12), rcv(0000), exp(0015)
adc_delay_1: sel(13), rcv(0000), exp(0015)
adc_delay_1: sel(14), rcv(0000), exp(0015)
adc_delay_1: sel(15), rcv(0000), exp(0015)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0016)
adc_delay_1: sel(10), rcv(0000), exp(0016)
adc_delay_1: sel(11), rcv(0000), exp(0016)
adc_delay_1: sel(12), rcv(0000), exp(0016)
adc_delay_1: sel(13), rcv(0000), exp(0016)
adc_delay_1: sel(14), rcv(0000), exp(0016)
adc_delay_1: sel(15), rcv(0000), exp(0016)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0017)
adc_delay_1: sel(10), rcv(0000), exp(0017)
adc_delay_1: sel(11), rcv(0000), exp(0017)
adc_delay_1: sel(12), rcv(0000), exp(0017)
adc_delay_1: sel(13), rcv(0000), exp(0017)
adc_delay_1: sel(14), rcv(0000), exp(0017)
adc_delay_1: sel(15), rcv(0000), exp(0017)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0018)
adc_delay_1: sel(10), rcv(0000), exp(0018)
adc_delay_1: sel(11), rcv(0000), exp(0018)
adc_delay_1: sel(12), rcv(0000), exp(0018)
adc_delay_1: sel(13), rcv(0000), exp(0018)
adc_delay_1: sel(14), rcv(0000), exp(0018)
adc_delay_1: sel(15), rcv(0000), exp(0018)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(0019)
adc_delay_1: sel(10), rcv(0000), exp(0019)
adc_delay_1: sel(11), rcv(0000), exp(0019)
adc_delay_1: sel(12), rcv(0000), exp(0019)
adc_delay_1: sel(13), rcv(0000), exp(0019)
adc_delay_1: sel(14), rcv(0000), exp(0019)
adc_delay_1: sel(15), rcv(0000), exp(0019)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(001A)
adc_delay_1: sel(10), rcv(0000), exp(001A)
adc_delay_1: sel(11), rcv(0000), exp(001A)
adc_delay_1: sel(12), rcv(0000), exp(001A)
adc_delay_1: sel(13), rcv(0000), exp(001A)
adc_delay_1: sel(14), rcv(0000), exp(001A)
adc_delay_1: sel(15), rcv(0000), exp(001A)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(001B)
adc_delay_1: sel(10), rcv(0000), exp(001B)
adc_delay_1: sel(11), rcv(0000), exp(001B)
adc_delay_1: sel(12), rcv(0000), exp(001B)
adc_delay_1: sel(13), rcv(0000), exp(001B)
adc_delay_1: sel(14), rcv(0000), exp(001B)
adc_delay_1: sel(15), rcv(0000), exp(001B)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(001C)
adc_delay_1: sel(10), rcv(0000), exp(001C)
adc_delay_1: sel(11), rcv(0000), exp(001C)
adc_delay_1: sel(12), rcv(0000), exp(001C)
adc_delay_1: sel(13), rcv(0000), exp(001C)
adc_delay_1: sel(14), rcv(0000), exp(001C)
adc_delay_1: sel(15), rcv(0000), exp(001C)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(001D)
adc_delay_1: sel(10), rcv(0000), exp(001D)
adc_delay_1: sel(11), rcv(0000), exp(001D)
adc_delay_1: sel(12), rcv(0000), exp(001D)
adc_delay_1: sel(13), rcv(0000), exp(001D)
adc_delay_1: sel(14), rcv(0000), exp(001D)
adc_delay_1: sel(15), rcv(0000), exp(001D)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(001E)
adc_delay_1: sel(10), rcv(0000), exp(001E)
adc_delay_1: sel(11), rcv(0000), exp(001E)
adc_delay_1: sel(12), rcv(0000), exp(001E)
adc_delay_1: sel(13), rcv(0000), exp(001E)
adc_delay_1: sel(14), rcv(0000), exp(001E)
adc_delay_1: sel(15), rcv(0000), exp(001E)
pcore_version: 10
adc_delay_1: sel( 9), rcv(0000), exp(001F)
adc_delay_1: sel(10), rcv(0000), exp(001F)
adc_delay_1: sel(11), rcv(0000), exp(001F)
adc_delay_1: sel(12), rcv(0000), exp(001F)
adc_delay_1: sel(13), rcv(0000), exp(001F)
adc_delay_1: sel(14), rcv(0000), exp(001F)
adc_delay_1: sel(15), rcv(0000), exp(001F)
pcore_version: 10
adc_setup: can not set a zero error delay!
Beginning testing.
ADC Test: mode - MIDSCALE
format - OFFSET BINARY
ERROR[ 0]: rcv(C0008000), exp(80008000)
ERROR[ 1]: rcv(C000C000), exp(80008000)
ERROR[ 2]: rcv(C000C000), exp(80008000)
ERROR[ 3]: rcv(C000C000), exp(80008000)
ERROR[ 4]: rcv(C000C000), exp(80008000)
ERROR[ 5]: rcv(C000C000), exp(80008000)
ERROR[ 6]: rcv(C000C000), exp(80008000)
ERROR[ 7]: rcv(C000C000), exp(80008000)
ERROR[ 8]: rcv(C000C000), exp(80008000)
ERROR[ 9]: rcv(C000C000), exp(80008000)
ERROR[10]: rcv(C000C000), exp(80008000)
ERROR[11]: rcv(C000C000), exp(80008000)
ERROR[12]: rcv(C000C000), exp(80008000)
ERROR[13]: rcv(C000C000), exp(80008000)
ERROR[14]: rcv(C000C000), exp(80008000)
ERROR[15]: rcv(C000C000), exp(80008000)
ERROR[16]: rcv(8000C000), exp(80008000)
ERROR[17]: rcv(00000000), exp(80008000)
ERROR[18]: rcv(00000000), exp(80008000)
ERROR[19]: rcv(00000000), exp(80008000)
ERROR[20]: rcv(00000000), exp(80008000)
ERROR[21]: rcv(00000000), exp(80008000)
ERROR[22]: rcv(00000000), exp(80008000)
ERROR[23]: rcv(00000000), exp(80008000)
ERROR[24]: rcv(00008000), exp(80008000)
ERROR[31]: rcv(FF00C000), exp(80008000)
ADC Test: mode - MIDSCALE
format - TWOS_COMPLEMENT
ERROR[31]: rcv(FF000000), exp(00000000)
ADC Test: mode - POS_FULLSCALE
format - OFFSET BINARY
ERROR[ 0]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[ 1]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[ 2]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[ 3]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[ 4]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[ 5]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[ 6]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[ 7]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[ 8]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[ 9]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[10]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[11]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[12]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[13]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[14]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[15]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[16]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[17]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[18]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[19]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[20]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[21]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[22]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[23]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[24]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[25]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[26]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[27]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[28]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[29]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[30]: rcv(FFCFFFCF), exp(FFFFFFFF)
ERROR[31]: rcv(FFCFFFCF), exp(FFFFFFFF)
ADC Test: mode - POS_FULLSCALE
format - TWOS_COMPLEMENT
ERROR[ 0]: rcv(FFCFFFCF), exp(7FFF7FFF)
ERROR[ 1]: rcv(FFCFFFCF), exp(7FFF7FFF)
ERROR[ 2]: rcv(7FCFFFCF), exp(7FFF7FFF)
ERROR[ 3]: rcv(7FCF7FCF), exp(7FFF7FFF)
ERROR[ 4]: rcv(7FCF7FCF), exp(7FFF7FFF)
ERROR[ 5]: rcv(7FCF7FCF), exp(7FFF7FFF)
ERROR[ 6]: rcv(7FCF7FCF), exp(7FFF7FFF)
ERROR[ 7]: rcv(7FCF7FCF), exp(7FFF7FFF)
ERROR[ 8]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[ 9]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[10]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[11]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[12]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[13]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[14]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[15]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[16]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[17]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[18]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[19]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[20]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[21]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[22]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[23]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[24]: rcv(3FCF3FCF), exp(7FFF7FFF)
ERROR[25]: rcv(FFCF7FCF), exp(7FFF7FFF)
ERROR[26]: rcv(FFCFFFCF), exp(7FFF7FFF)
ERROR[27]: rcv(FFCFFFCF), exp(7FFF7FFF)
ERROR[28]: rcv(FFCFFFCF), exp(7FFF7FFF)
ERROR[29]: rcv(FFCFFFCF), exp(7FFF7FFF)
ERROR[30]: rcv(FFCFFFCF), exp(7FFF7FFF)
ERROR[31]: rcv(FFCFFFCF), exp(7FFF7FFF)
ADC Test: mode - NEG_FULLSCALE BINARY
format - OFFSET BINARY
ERROR[31]: rcv(FF000000), exp(00000000)
ADC Test: mode - NEG_FULLSCALE BINARY
format - TWOS_COMPLEMENT
ERROR[ 0]: rcv(00000000), exp(80008000)
ERROR[ 1]: rcv(00000000), exp(80008000)
ERROR[ 2]: rcv(00008000), exp(80008000)
ERROR[ 8]: rcv(C0008000), exp(80008000)
ERROR[ 9]: rcv(C000C000), exp(80008000)
ERROR[10]: rcv(C000C000), exp(80008000)
ERROR[11]: rcv(C000C000), exp(80008000)
ERROR[12]: rcv(C000C000), exp(80008000)
ERROR[13]: rcv(C000C000), exp(80008000)
ERROR[14]: rcv(C000C000), exp(80008000)
ERROR[15]: rcv(C000C000), exp(80008000)
ERROR[16]: rcv(C000C000), exp(80008000)
ERROR[17]: rcv(C000C000), exp(80008000)
ERROR[18]: rcv(C000C000), exp(80008000)
ERROR[19]: rcv(C000C000), exp(80008000)
ERROR[20]: rcv(C000C000), exp(80008000)
ERROR[21]: rcv(C000C000), exp(80008000)
ERROR[22]: rcv(C000C000), exp(80008000)
ERROR[23]: rcv(C000C000), exp(80008000)
ERROR[24]: rcv(C000C000), exp(80008000)
ERROR[25]: rcv(8000C000), exp(80008000)
ERROR[26]: rcv(00000000), exp(80008000)
ERROR[27]: rcv(00000000), exp(80008000)
ERROR[28]: rcv(00000000), exp(80008000)
ERROR[29]: rcv(00000000), exp(80008000)
ERROR[30]: rcv(00000000), exp(80008000)
ERROR[31]: rcv(FF000000), exp(80008000)
ADC Test: mode - CHECKERBOARD
format - OFFSET BINARY
ERROR[ 0]: rcv(5545AA8A), exp(AAAA5555)
ERROR[ 1]: rcv(5545AA8A), exp(AAAA5555)
ERROR[ 2]: rcv(5544AA8B), exp(AAAA5555)
ERROR[ 3]: rcv(1500EACB), exp(AAAA5555)
ERROR[ 4]: rcv(1000EFCF), exp(AAAA5555)
ERROR[ 5]: rcv(1000FFCF), exp(AAAA5555)
ERROR[ 6]: rcv(0000EFCF), exp(AAAA5555)
ERROR[ 7]: rcv(AA8A5545), exp(AAAA5555)
ERROR[ 8]: rcv(AA8A5545), exp(AAAA5555)
ERROR[ 9]: rcv(AA8A5545), exp(AAAA5555)
ERROR[10]: rcv(AA8A5545), exp(AAAA5555)
ERROR[11]: rcv(AA8A5545), exp(AAAA5555)
ERROR[12]: rcv(AA8A5545), exp(AAAA5555)
ERROR[13]: rcv(AA8A5545), exp(AAAA5555)
ERROR[14]: rcv(AA8A5545), exp(AAAA5555)
ERROR[15]: rcv(AA8A5545), exp(AAAA5555)
ERROR[16]: rcv(AA8A5545), exp(AAAA5555)
ERROR[17]: rcv(AA8A5545), exp(AAAA5555)
ERROR[18]: rcv(AA8A5545), exp(AAAA5555)
ERROR[19]: rcv(AA8A5545), exp(AAAA5555)
ERROR[20]: rcv(AA8A5545), exp(AAAA5555)
ERROR[21]: rcv(AA8A5545), exp(AAAA5555)
ERROR[22]: rcv(AA8A5545), exp(AAAA5555)
ERROR[23]: rcv(0000FFCF), exp(AAAA5555)
ERROR[24]: rcv(0000FFCF), exp(AAAA5555)
ERROR[25]: rcv(AA8A5545), exp(AAAA5555)
ERROR[26]: rcv(AA8A5545), exp(AAAA5555)
ERROR[27]: rcv(AA8A5545), exp(AAAA5555)
ERROR[28]: rcv(AA8A5545), exp(AAAA5555)
ERROR[29]: rcv(AA8A5545), exp(AAAA5555)
ERROR[30]: rcv(AA8A5545), exp(AAAA5555)
ERROR[31]: rcv(FFCB5545), exp(AAAA5555)
ADC Test: mode - CHECKERBOARD
format - TWOS_COMPLEMENT
ERROR[ 0]: rcv(5545AA8A), exp(AAAA5555)
ERROR[ 1]: rcv(5545AA8A), exp(AAAA5555)
ERROR[ 2]: rcv(5544AA8B), exp(AAAA5555)
ERROR[ 3]: rcv(1500EACB), exp(AAAA5555)
ERROR[ 4]: rcv(1004EFCF), exp(AAAA5555)
ERROR[ 5]: rcv(1000FF0F), exp(AAAA5555)
ERROR[ 6]: rcv(0000EFCF), exp(AAAA5555)
ERROR[ 7]: rcv(AA8A5545), exp(AAAA5555)
ERROR[ 8]: rcv(AA8A5545), exp(AAAA5555)
ERROR[ 9]: rcv(AA8A5545), exp(AAAA5555)
ERROR[10]: rcv(AA8A5545), exp(AAAA5555)
ERROR[11]: rcv(AA8A5545), exp(AAAA5555)
ERROR[12]: rcv(AA8A5545), exp(AAAA5555)
ERROR[13]: rcv(AA8A5545), exp(AAAA5555)
ERROR[14]: rcv(AA8A5545), exp(AAAA5555)
ERROR[15]: rcv(AA8A5545), exp(AAAA5555)
ERROR[16]: rcv(AA8A5545), exp(AAAA5555)
ERROR[17]: rcv(AA8A5545), exp(AAAA5555)
ERROR[18]: rcv(AA8A5545), exp(AAAA5555)
ERROR[19]: rcv(AA8A5545), exp(AAAA5555)
ERROR[20]: rcv(AA8A5545), exp(AAAA5555)
ERROR[21]: rcv(AA8A5545), exp(AAAA5555)
ERROR[22]: rcv(AA8A5545), exp(AAAA5555)
ERROR[23]: rcv(00005545), exp(AAAA5555)
ERROR[24]: rcv(0000FFCF), exp(AAAA5555)
ERROR[25]: rcv(228AFFCF), exp(AAAA5555)
ERROR[26]: rcv(E70E5545), exp(AAAA5555)
ERROR[27]: rcv(9686358F), exp(AAAA5555)
ERROR[28]: rcv(AA8A7545), exp(AAAA5555)
ERROR[29]: rcv(55450000), exp(AAAA5555)
ERROR[30]: rcv(5545AA8A), exp(AAAA5555)
ERROR[31]: rcv(FF45AA8A), exp(AAAA5555)
ADC Test: mode - PN_23_SEQUENCE
format - OFFSET BINARY
ERROR: PN status(0002).
ADC Test: mode - PN_23_SEQUENCE
format - TWOS_COMPLEMENT
Test skipped
ADC Test: mode - PN_9_SEQUENCE
format - OFFSET BINARY
ERROR: PN status(0002).
ADC Test: mode - PN_9_SEQUENCE
format - TWOS_COMPLEMENT
Test skipped
ADC Test: mode - ONE_ZERO_TOGGLE
format - OFFSET BINARY
ERROR[ 0]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 1]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 2]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 3]: rcv(FFCF5545), exp(FFFF0000)
ERROR[ 4]: rcv(FFCFAA8A), exp(FFFF0000)
ERROR[ 5]: rcv(0000FFCF), exp(FFFF0000)
ERROR[ 6]: rcv(4400FFCF), exp(FFFF0000)
ERROR[ 7]: rcv(AA8A0A8A), exp(FFFF0000)
ERROR[ 8]: rcv(554DA88A), exp(FFFF0000)
ERROR[ 9]: rcv(EE8AFFCF), exp(FFFF0000)
ERROR[10]: rcv(5FCFA00A), exp(FFFF0000)
ERROR[11]: rcv(EA8AFFCF), exp(FFFF0000)
ERROR[12]: rcv(7FCFA008), exp(FFFF0000)
ERROR[13]: rcv(AA8AFFCF), exp(FFFF0000)
ERROR[14]: rcv(FFCF0000), exp(FFFF0000)
ERROR[15]: rcv(FFCF0000), exp(FFFF0000)
ERROR[16]: rcv(FFCF0000), exp(FFFF0000)
ERROR[17]: rcv(FFCF0000), exp(FFFF0000)
ERROR[18]: rcv(AA8A5545), exp(FFFF0000)
ERROR[19]: rcv(55450000), exp(FFFF0000)
ERROR[20]: rcv(5545AA8A), exp(FFFF0000)
ERROR[21]: rcv(5545AA8A), exp(FFFF0000)
ERROR[22]: rcv(5545AA8A), exp(FFFF0000)
ERROR[23]: rcv(5545AA8A), exp(FFFF0000)
ERROR[24]: rcv(5545AA8A), exp(FFFF0000)
ERROR[25]: rcv(5545AA8A), exp(FFFF0000)
ERROR[26]: rcv(5545AA8A), exp(FFFF0000)
ERROR[27]: rcv(5545AA8A), exp(FFFF0000)
ERROR[28]: rcv(5545AA8A), exp(FFFF0000)
ERROR[29]: rcv(5545AA8A), exp(FFFF0000)
ERROR[30]: rcv(5545AA8A), exp(FFFF0000)
ERROR[31]: rcv(FF45AA8A), exp(FFFF0000)
ADC Test: mode - ONE_ZERO_TOGGLE
format - TWOS_COMPLEMENT
ERROR[ 0]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 1]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 2]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 3]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 4]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 5]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 6]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 7]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 8]: rcv(AA8A5545), exp(FFFF0000)
ERROR[ 9]: rcv(AA8A5545), exp(FFFF0000)
ERROR[10]: rcv(AA8A5545), exp(FFFF0000)
ERROR[11]: rcv(AA8A5545), exp(FFFF0000)
ERROR[12]: rcv(AA8A5545), exp(FFFF0000)
ERROR[13]: rcv(55450000), exp(FFFF0000)
ERROR[14]: rcv(FFCF0000), exp(FFFF0000)
ERROR[15]: rcv(FFCF0000), exp(FFFF0000)
ERROR[16]: rcv(5545FDCF), exp(FFFF0000)
ERROR[17]: rcv(EE8ADFCF), exp(FFFF0000)
ERROR[18]: rcv(5FCDA08A), exp(FFFF0000)
ERROR[19]: rcv(EE8AFFCF), exp(FFFF0000)
ERROR[20]: rcv(5FCFA00A), exp(FFFF0000)
ERROR[21]: rcv(EE8AFFCF), exp(FFFF0000)
ERROR[22]: rcv(5FCFA08A), exp(FFFF0000)
ERROR[23]: rcv(0000FFCF), exp(FFFF0000)
ERROR[24]: rcv(0000FFCF), exp(FFFF0000)
ERROR[25]: rcv(0000FFCF), exp(FFFF0000)
ERROR[26]: rcv(5545FFCF), exp(FFFF0000)
ERROR[27]: rcv(0000AA8A), exp(FFFF0000)
ERROR[28]: rcv(AA8A5545), exp(FFFF0000)
ERROR[29]: rcv(AA8A5545), exp(FFFF0000)
ERROR[30]: rcv(AA8A5545), exp(FFFF0000)
ERROR[31]: rcv(FF8A5545), exp(FFFF0000)
Testing done.
Start capturing data...
Done.

 

In addition, I have also tested the zedboard 2017_r1 reference design on a zedboard, and yielded familiar error messages, but less of it as shown below.

********************************************************************
ADI AD9467-FMC-EBZ Reference Design
AD9467 CHIP ID: 0x50
AD9467 CHIP GRADE: 0x20
AD9517 CHIP ID: 0xD3
********************************************************************
AD9467[0x016]: 00
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
pcore_version: 10
adc_delay: setting zero error delay (18)
pcore_version: 10
ADC Test: mode - MIDSCALE
format - OFFSET BINARY
ERROR[31]: rcv(D0008000), exp(80008000)
ADC Test: mode - MIDSCALE
format - TWOS_COMPLEMENT
ERROR[31]: rcv(D0000000), exp(00000000)
ADC Test: mode - POS_FULLSCALE
format - OFFSET BINARY
ERROR[31]: rcv(D0FFFFFF), exp(FFFFFFFF)
ADC Test: mode - POS_FULLSCALE
format - TWOS_COMPLEMENT
ERROR[31]: rcv(D0FF7FFF), exp(7FFF7FFF)
ADC Test: mode - NEG_FULLSCALE BINARY
format - OFFSET BINARY
ERROR[31]: rcv(D0000000), exp(00000000)
ADC Test: mode - NEG_FULLSCALE BINARY
format - TWOS_COMPLEMENT
ERROR[31]: rcv(D0008000), exp(80008000)
ADC Test: mode - CHECKERBOARD
format - OFFSET BINARY
ERROR[31]: rcv(D0AA5555), exp(AAAA5555)
ADC Test: mode - CHECKERBOARD
format - TWOS_COMPLEMENT
ERROR[31]: rcv(D055AAAA), exp(5555AAAA)
ADC Test: mode - PN_23_SEQUENCE
format - OFFSET BINARY
Test passed
ADC Test: mode - PN_23_SEQUENCE
format - TWOS_COMPLEMENT
Test skipped
ADC Test: mode - PN_9_SEQUENCE
format - OFFSET BINARY
Test passed
ADC Test: mode - PN_9_SEQUENCE
format - TWOS_COMPLEMENT
Test skipped
ADC Test: mode - ONE_ZERO_TOGGLE
format - OFFSET BINARY
ERROR[31]: rcv(D0FF0000), exp(FFFF0000)
ADC Test: mode - ONE_ZERO_TOGGLE
format - TWOS_COMPLEMENT
ERROR[31]: rcv(D0FF0000), exp(FFFF0000)
Testing done.
Start capturing data...
Done.

 

This leads to my question, do the failed tests affect the functionality of the ADC, and if so, I would appreciate any suggestions and questions to allow me to solve this.

 

Regards

Outcomes