Can the AD9371 ADC and DAC converter clocks run at lower sample rates than the AD9371 JESD core clock? I assume, if so, that the multiple will be 1x, 2x, 4x, how high can this multiple go?
Clock rates are as below. (Ref https://wiki.analog.com/resources/eval/user-guides/mykonos/software/filters )
JESD high speed serial lane rates range from 614.4 Mbps to 6144 Mbps.
Receive: After ADC we have Dec5 (X5) ,HB1 (X2) and FIR (X4), so max decimation is 5x2x4= 40
Transmit: We have FIR (X4) , THB1(X2), THB2(X2) before DAC. Max interpolation possible is 4x2x2 = 16
Please refer UG-992 , Rx signal path example for more details (page 165).
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