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Optimising data transfer from FPGA to the software

Question asked by mmilosavljevic on Jul 31, 2017
Latest reply on Aug 10, 2017 by larsc

Dear Support Team,


I have inserted my own IP into the existing HDL design from the Analog Devices and adapted it to my custom board. I am only concern in receiving samples so the DAC chain is left as it is. So the connection is:


ADC AD9361 IP > adc_fifo > Custom IP > adc_pack > adi dma


All works good! 


But when reading the samples in real time using the IIO i get some samples lost as the processor cannot keep up with the buffer refilling. Again, i need all this to happen in real time.


My relevant data (frame) contains 14 bytes only and i extract those bytes from the iio buffer when there is a valid flag (ie. valid message). But to get those 14 bytes i have to read thousands of samples from the buffer to get my 14 bytes (this is because the buffer is constantly refilled and i have no means to tell it to refill only at specific time instance as i dont know when is the valid flag). In other words if for example i set the buffer size to 4M samples i need to go through all those samples (in a for loop for instance) in order to extract my message even if there are maybe 1 or 2 valid messages in that buffer. Of course, i can reduce the buffer size but that doesnt help much as i will increase the overhead. 


What i really would like to be able to do is to only send the message to the buffer when that valid flag is up. I wouldnt want anything else to be sent in the meantime. This way i can significantly reduce the buffer size and make the system more optimal for real time application that i have. 


So my question is, I dont necessary fully understand how the ADC_PACK works but what is the best way to achieve that? Can this be done? Do I need to modify the ADC_PACK IP? Or can i do it more efficiently in the software?


Any comments/suggestions will be appreciated.


Many thanks