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AD9364 Xilinx (Vivado) axi_ad9163 Timing Constraints

Question asked by GeoffreyM on Jul 31, 2017
Latest reply on Aug 1, 2017 by larsc

Hi there. I am having trouble defining timing constraints (Vivado 15.4, z7045 on zc706 evb) for the AD9364 digital interface. I am using the CMOS interface, have imported the Verilog into a piece of custom IP, but am having difficulty with the DDR interface. I need to operate DDR, since my bandwidth is 56MHz, and am open to using also the LVDS option, although, having only 7 cm of trace, I suspect CMOS should be reliable.

 

 

The timing diagrams in the reference manual suggest to me that the falling edge of rx_clk_in, followed by the rising edge, might be the appropriate way to acquire data, offering ample setup time, data able to be delayed by the IDELAYE2 primitive to guarantee hold time. However, the IP uses the rising edge. Delay to the clock is not implemented, suggesting stale data might be exchanged at the beginning of a burst. In CMOS mode, the device operates at the relatively low frequency of 61.44MHz, so timing should not be particularly critical. Are the constraints available, or a trade secret? :-) I notice the data is qualified, in CMOS mode, 1R1T, on both phases of rx_frame_in, 10 and 01. Can somebody explain this?

 

 

I am also puzzled by the transmit path. The valid signal does not seem to be forwarded coherently with the data, bypassing the IQ correction, for example. The receive path is implemented as expected. My system architecture requires the DMA interface to be substituted with a pair of asynchronous AXI4 stream FIFO's, clocked with lclk in the device domain, valid on the rx side corresponding with tvalid. On the tx side, it appears that valid data is signalled to the device interface before it has been processed, the valid signal otherwise being seemingly configurable as tready.

 

On the other end of the FIFOs, the rx and tx streams run at 100MHz, so should maintain the feed and consumption of data. They are standard Xilinx AXI4 stream FIFOs. These are stallable from the core, but not able to stall it, other means being used to enable transmission and reception. The FIFOs form the start and end points of typical COFDM signal paths.

 

 

Best regards

Geoff

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