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ADV7842 VBI Being Blurred

Question asked by DRC on Oct 21, 2011
Latest reply on Nov 30, 2011 by mattp

Hi,

 

I'm trying to get VBI pass-through to work properly.

 

My input is an NTSC CVBS signal generated by an ADV7341, with actual image data in the VBI.  This allows me to test clearly if the ADV7842 is passing the VBI through by simply capturing the VBI and looking at the video to see if it looks right.  The test signal has 256 lines of image (non-black) per field, for a total of 512 lines per frame.  On each field, this works out to about 12-16 extra VBI lines captured above active.

 

I have enabled VBI pass-through in the ADV7842 using the following registers:

 

[SDPIOMap][0xB0][7] = 0 (SDP_VBLANK_EN)

[SDPIOMap][0xB0][6] = 0 (SDP_HBLANK_EN)

[SDPMap][0x18][7] = 0 (SDP_BLANK_C_VBI)

 

The pass-through mostly seems to be working.  The 5 lines of VBI just before active, on each field, look fine.  However, above those 5 lines, the ADV7842 is blurring the video (see attachment color_bars.bmp).

 

I noticed that if I set SDP_BLANK_C_VBI = 1, which instructs the ADV7842 to kill the colour in the VBI, it does it exactly for the lines that are being blurred (see attachment color_bars_top_lines_no_c.bmp) and not for the whole VBI.  So in this case, it considers "VBI" to be just those upper lines.

 

If I set SDP_VBLANK_EN = 1, it blacks out the entire VBI properly.  So in this case, it considers "VBI" to be the proper VBI.

 

So the ADV7842 is doing something special for those upper lines.  Why is it distorting those lines and how do I get it to stop?

 

I have confirmed that the input signal is good by capturing it using of my other boards with an ADV7403 -- I am able to clearly see the VBI image with no blurring.

 

The script I used is shown below.  It's based on an example with some modifications.

 

Thanks

 

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;1-1e CVBS NTSC_PAL-M  480i H_V_DE 36bit 444 out HDMI:
Device "ADV7842" Instance 1 Bank "IOMap"
Write Offset 00 Data 01 ; CVBS 4x1 mode
Write Offset 01 Data 00 ; SD core
Write Offset "IO_REG_03" Bitfield "OP_FORMAT_SEL" Data 42     ; Set output mode to 36 bit 444
Write Offset "IO_REG_0C" Bitfield "POWER_DOWN" Data 0     ; Main power-up
Write Offset "IO_REG_0C" Bitfield "PADS_PDN" Data 0     ; Power-up digital outputs.  This can be used to tri-state the outputs.
Write Offset "IO_REG_0C" Bitfield "VDP_PDN" Data 1     ; Power-down the VBI Data Processor (VDP)
Write Offset "IO_REG_0C" Bitfield "CP_PWRDN" Data 1     ; Power-down the CP (not used for CVBS)
Write Offset "IO_REG_15" Bitfield "TRI_PIX" Data 0     ; Enable pixel output data bus
Write Offset "IO_REG_15" Bitfield "TRI_LLC" Data 0     ; Enable LLC pixel clock output
Write Offset "IO_REG_15" Bitfield "TRI_SYNCS" Data 0     ; Enable HVF sync outputs
Write Offset "IO_REG_15" Bitfield "TRI_AUDIO" Data 0     ; Enable audio outputs (in case HDMI audio needs to be captured)
Write Offset "IO_REG_15" Bitfield "TRI_SYNC_OUT" Data 1     ; SYNC_OUT is not used
Write Offset 05 Bitfield 1 Data 1     ; Enable AV code replication on all channels.  Set to 1 for SDP
Device "ADV7842" Instance 1 Bank "AFEMap"
Write Offset 0C Data 1F ; ADI recommended write
Write Offset 12 Data 63 ; ADI recommended write
Write Offset 00 Data 0E ; ADC0 power Up
Write Offset "INPUT_MUX_CONTROL_1" Bitfield "ADC_SWITCH_MAN" Data 1      ; Enable manual control of input analog muxes (required for CVBS input).  AIN_SEL is overridden.
Write Offset "INPUT_MUX_CONTROL_2" Bitfield "ADC0_SW_MAN" Data B     ; Set ADC0 source to Ain11 (this is the input pin that CVBS is connected to)
Write Offset 01 Data 06 ; Set to default value.  This reg is undocumented.
Device "ADV7842" Instance 1 Bank "SDPMap"
Write Offset "AUTODETECT_ENABLES" Data FF               ; Enable auto-detection of all SD formats
Write Offset "SDP_FREE_RUN" Bitfield "SDP_FREE_RUN_AUTO" Data 0     ; Disable free-run (ie. ADV7842 output will be killed if there's no valid input).
Device "ADV7842" Instance 1 Bank "SDPIOMap"
Write Offset 7A Data A5 ; Timing Adjustment
Write Offset 7B Data 8F ; Timing Adjustment
Write Offset 60 Data 01 ; SDRAM reset
Write Offset 97 Data 00 ; Hsync width Adjustment
Write Offset B2 Bitfield 3 Data 1 ; Enable EAV
Write Offset B2 Bitfield 2 Data 1 ; Enable SAV
Write Offset B0 Bitfield 7 Data 0 ; Do not blank during VBI
Write Offset B0 Bitfield 6 Data 0 ; Do not blank during HBI
Write Offset "EAV_POSITION_2" Bitfield "SDP_EAV_POS_ADJ" Data 7
Write Offset "SAV_POSITION_2" Bitfield "SDP_SAV_POS_ADJ" Data 7
Device "ADV7842" Instance 1 Bank "SDPMap"
Write Offset 00 Data 7F ; Autodetect PAL NTSC SECAM
Write Offset 01 Data 00 ; Pedestal Off
Write Offset 03 Data E4 ; Manual VCR Gain Luma 0x40B
Write Offset 04 Data 0B ; Manual Luma setting
Write Offset 05 Data C3 ; Manual Chroma setting 0x3FE
Write Offset 06 Data FE ; Manual Chroma setting
Write Offset 12 Data 05 ; Frame TBC,3D comb enabled
Write Offset A7 Data 00 ; ADI Recommended Write
Write Offset 18 Bitfield 7 Data 0 ; Do not blank Cb/Cr during VBI

 

 

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