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Details of FPGA implementation in FMCDAQ2 design

Question asked by stevereine Employee on Jul 27, 2017
Latest reply on Aug 7, 2017 by rejeesh

In the attached document, and with reference to the HDL code given in the link below, widths of the data stream are given at various places in the signal chain. For instance, the data going into the BRAM FIFO is given as 128 bits wide at 100MHz. This customer would like specific details on the optimum point in the design in which to inject a stream of uninterrupted DAC data, and at that point in the signal chain the exact format of the data.  That includes how the data is broken up (on a byte basis or 16 bit boundaries, where the LSB and MSB end up, the DAC lane assignment, the temporal order of the samples, anything else we haven’t considered?).  Also need to know which  specific signal names in the design are involved, including data busses and how to break or drive any control signals.

 

 https://github.com/analogdevicesinc/hdl

 

thanks,

 

Steve

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