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ADXL372 Noise

Question asked by kurth on Jul 27, 2017
Latest reply on Aug 4, 2017 by NevadaMark

I am using the ADXL372 as follows:

 

   6400 Hz ODR using external precision 614.4 kHz clock.

   Streaming acquisition of XYZ samples to the FIFO

   ~15 Hz HPF, 3200 Hz LPF

   8 MHz SPI connection to MCU

 

This is a clean 4-layer board with power supplied from batteries and a LDO.

The VDDIO pin is isolated with a ferrite bead and each power pin is bypassed with a 1 uF and 0.1 uF ceramic cap.

If I acquire data on a stable surface, I see peak outputs on the accelerometers exceeding 1G, but a long average of the data is ~0. An FFT of the data shows two peaks at 1280 Hz & 2560 Hz, with peak amplitudes of 0.1G to 0.3G, depending on the channel. Is this internal clock leakage? I can't find any spec for clock leakage in the datasheet, so I don't know what to expect. Is this reasonable?

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