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Sample Frequency Offset between ADC and DAC

Question asked by RobertYJ on Jul 27, 2017
Latest reply on Jul 28, 2017 by travisfcollins

I am using two AD9361 FMCOMMS3 as the transmitter and receiver to send the 802.11a packet, and I found that when the length of packet become longer will cause the packet error rate higher.


After I do some test and research I know that is caused by the sample frequency offset between the transmitter's DAC and receiver's ADC.


I know these two FIR Filter is a poly-phase FIR Filter, can this filter solve this problem?


{1280000000 , 160000000 , 80000000 , 40000000 , 20000000 , 20000000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies
{1280000000 , 160000000 , 80000000 , 40000000 , 20000000 , 20000000},//uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies


Above is the data path I used.


Thanks a lot!!