In the datasheet P10 BW_SEL (BANDWIDTH SELECTION) MODE.
Driving the BW_SEL input signal to logic high, the amplifier provides a 3.8 GHz bandwidth. Driving the BW_SEL input
signal to logic low, the amplifier accepts input signals through a 1.5 GHz, 2-pole, low-pass filter that improves receiving
The low-pass filter reduces the possible relaxation oscillation of low speed, low cost laser source by limiting the input signal bandwidth.
The BW_SEL pin has a 100 kΩ, on-chip pull-up resistor. Setting the BW_SEL pin open disables the low-pass filter.
But AN-761 ADN2892 Evaluation Board P2.
Driving the BW_SEL input to logic high will enable the internal 1.5 GHz low-pass filter. Switch S5 should be left
in the factory default setting position (Logic 0) for normal operation up to 4.25 Gbps or at the upper position
(Logic 1) to enable the on-chip low-pass filter.
Is the application note inconsistent with the data sheet?