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AD9683 JESD204B link is ready bit

Question asked by hydravliska on Jul 27, 2017
Latest reply on Jul 31, 2017 by hydravliska

Hello everyone

 

I am currently evaluating the AD9683 on a custom HW and have problems getting the data transmission going.

The FPGA seems to not properly receive the data from the ADC or at least I am not able to interpret the incoming data stream. I have used the SPI interface to debug the status flags of the AD9683 and have a question regarding a special bit.
When reading register 0x0A "PLL status" I get the value 0x81. A quick look in the datasheet tells that both "PLL locked status" and "JESD204B link is ready" bits are asserted. How is the later flag specified? What does "link is ready" mean? Does it mean that all the three SYNC phases have been completed (CGS, ILAS and Data transmission)?

 

I also tried to activate the "Test Mode Cycle" (register 0x0D) but I was not sure if I did it properly. I couldn't find the expected pattern in the RX stream of the FPGA transceiver. Could someone provide me with a quick explanation how the test mode is activated.

 

The AD9683 datasheet specifies a maximum lane rate of 5 Gbps (AD9683-250). I assume this is the total bandwidth together with the 8b/10b? The FPGA is also configured for 5Gbps. The ADC receives a reference clock of 250MHz (CLK+-) and the FPGA Transceiver receives a 125MHz reference. This should not be an issue I guess because both clocks are generated by a clock generator HW so they are related (common source)?

 

I was able to track the behavior of the transceiver and saw that a link is established for a short time (the FPGA claims that IDLE characters have been received) but at some later time the elastic buffer within the transceiver signals Overflow. The AD9683 datasheet chapter "JESD204B Synchronization Details" tells that the ADC transmits /K28.5/ during the CGS phase. Does this mean that every character sent has this value? The Xilinx IP Core has a 32-bit data interface so I would expect that the output of the IP Core should be 0xBCBCBCBC during this phase. Or am I totally wrong on that?

 

Any hints or tips would be much appreciated.

 

FPGA: a Kintex-7 implement the Xilinx JESD204B IP Core

SW: Vivado 2016.3

 

Regards,

Valko

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