As a background, I am currently trying to implement 802.11 WIFI in the AD9371+ZC706 evaluation board.And right now, my goal is to get my own AGC block to control the AD9371 attenuation through the GPIO.
I have already embedded my AGC block in the FPGA along with the AD9371 2016_R2 branch hardware and I would like to ask for advice how to connect the Zynq PL pins to the AD9371 GPIO pins. I am thinking of 2 possible ways to do this.
1. Output the AGC signal through a PMOD pin in ZC706 and connect by wire to the AD9371 GPIO pin.
2. Modify the FPGA GPIO pin assignment (ad9371_gpio_0(0/1)) corresponding to the AD9371 Manual GPIO signal pin (GPIO_(0/1)) to output my control signals instead.
I am currently favoring 2 so it wouldn't need any external components but I don't want to break anything in the API. Is it OK to sever the connection of the ad9371_gpio_0 and ad9371_gpio_1 from the BBP and let my AGC block in the PL control it directly.
Any thoughts or advice are welcome.