Hi,

I'm currently evaluating the use of the FIR Accelerator on a ADSP-SC584 to decimate an input signal. I found the following formula for FIR throughput:

(195 + 2 × N × 11 + W × (N/4+2) ) × C SCLK cycles

where

N is the Number of taps

W is the Window size

C is the Number of channels

This seems to be accurate for a decimation factor of M = 1 (i.e. no decimation).

Somewhere in the documentation it is written, that for a decimation factor of M > 1, the FIR Accelerator starts a new calculation only every Mth input sample. So inceasing M should not increase calculation time.

On the other hand, read data throughput is said to be two clock SCLK cycles per 32 bit word, so I would expect the total processing time to increase by 2 × W SCLK cycles for each increment of M. However this doesn't seem to be accurate. Testing with various parameters seems to indicate, that total time increases by 15 × W on each increment.

This would yield the following formula:

(195 + 2 × N × 11 + W × (N/4 + 2 + (M-1)×15) ) × C SCLK cycles

where

N is the Number of taps

W is the Window size

C is the Number of channels

M is the decimation factor

Is this formula correct, or am I doing something wrong?

Best regards,

Christoph

Since no one protested, I assume our performance evaluation was not totally wrong. Given the clear performance difference we saw in our tests, we habe decided to give up on the FIR Accelerator and just use the SHARC core.