I got a core hung (according to the VDSP error message) but I'm not sure what's the reason.
Following code fails
dm(m0,i0) = r3; //m0 is 0x200000 (DDR2 start address), i0 is 0...2000000
but this one works.
modify(i0,m0); //m0 is 0x200000 (DDR2 start address), i0 is 0...2000000
dm(i0,m5) = r3; //m5 is 0x0
I've enabled the SIMD mode in the MODE1 register in both cases.
The code is inside an SPORT irq routine.
In both cases I would expect that r3 is stored to address (i0+m0) and s3 is stored to address (i0+m0+1).