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Unstable jesd link initialization after changing sampling rate for ad9371

Question asked by dboyan on Jul 24, 2017

We're using adrv9371 boards in our design, which needs a sampling different from the one in the default no-os configuration. We have generated the correct profile and c code for our configuration, and managed to adapt ad9528 driver code to generate suitable clock frequencies. The configuration proves to be okay. However, we found the jesd link initialization of our configuration is not as reliable as the default one. We often see OrxFramerStatus = 0x20 (which is not a big problem for us because we're not using orx path for now), and sometimes we also see DeframerStatus = 0x61, which is indeed a problem since the Tx path becomes non-functional. The problem happens randomly, and it would come and go after reprogramming the FPGA.

What is the probable cause of the problem and how can I debug it?