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AD9517-4 SPI in FPGA by Verilog module

Question asked by Clark_Yao on Jul 22, 2017
Latest reply on Jul 25, 2017 by pkern

When using the FPGA (Zedboard Zynq Evaluation and Development Kit – xc7z0x0clg484-1) to control the AD9517-4(AD9467-FMC board) by SPI protocol in Verilog, I failed to send the command data and read out the registers’ data.

The whole project is with 25MHz SCLK, and the ILA is with the 100MHz sampling clock.

I Followed the AD9517-4  Data Sheet (page30 of 80) and suggestions on https://ez.analog.com/thread/96563, with internal VCO and Clock Distribution, as the internal VCO(0x010 = 8’b0110_1110) output is from 1450MHz to 1800MHz, and

REFIN/REFIN_N = 10MHz(differential reference mode, 0x1C = 8’b0000_0111), Vpp = 3.3,

R = 1(0x012 = 8’b0000_0000),

P = 16(0x016 = 8’b0000_0101),

A = 0(0x013 = 0000_0000),

B = 10(0x014 = 8’b0000_1010),

f_vco = 1600,

VCO_divider = 4(0x1E0 = 8’b0000_0010),

Divider2.1 = 2(0x199 = 8’b0000_0000),

Divider2.2 = 2(0x19B = 8’b0000_0000), bypassing the delay and without offset (default values),

choosing OUT5/OUT5_N mode(0x141 = 8’b0100_0010),

 the output should be 100MHz, but failed.

In order to read the register in SDO, commend the 0x000 = 8’b1011_1101.

The FPGA’s results (SDIO is the inout pin, CSB is the CS, SCLK is 25MHz)

 

With steps:(The attachement shows the detail steps with figures)

1. 0x000 = 8’b1011_1101 (set the SDO as the readback pin)(fig.1)
2. 0x232 = 8’b0000_0001(in order to make the SDO to work as data output pin, but failed as the SDO is 1’b1 all the time)(fig.2)
3. 0x010 = 0110_1110(choose the internal VCO and charge pump)(fig.3)
4. 0x012 = 8’b0000_0000(R = 1)(fig.4)
5. 0x13 = 8’b0000_0000(A = 0)(fig.5)
6. 0x014 = 8’b0000_1010(B = 10)(fig.6)
7. 0x016 = 8’b0000_0101(P=16)(fig.7)
8. 0x017 = 8’b1100_0100(status in differential reference when in differential mode, antibacklash pulse width 2.9 ns)(fig.8)
9.0x018 = 8’b0000_0110(VCO calibration, the 0x18[0] = 1’b0)(fig.9)
10. 0x1C = 8’b0000_0111(With REF1 and REF2 power on, differential reference mode)(fig.10)
11. 0x01D = 8’b0000_1100(Enables LD pin comparator and holdover), there is a question, the holdover must be disabled during the VCO calibration.
12. 0x1E0 = 8’b0000_0010(VCO divider = 4, default value)(fig.12)
13. 0x1E1 = 8’b0000_0010(Select the VCO as input to VCO divider)(fig.13)
14. 0x141 = 8’b0100_0010(Noninverting, LVDS 3.5 mA current, OUT5 power on)(fig.14)
15. 0x199 = 8’b0000_0000(set the Divider2.1 = 2)(fig.15)
16. 0x19A = 8’b0000_0000(Offset of Divider2.1 and Divider2.1 = 0)(fig.16)
17. 0x19B = 8’b0000_0000(Divider2.2 = 2)(fig.17)
18. 0x232 = 8’b0000_0001(update all registers)(fig.18)
19. 0x018 = 8’b0000_01111(VCO calibration, with 0x18[0] = 1’b1)(fig.19)
20. 0x232 = 8’b0000_0001(Update all registers)(fig.20)
21. Wait for 1390ns(from the rising edge to falling edge of AD9517_CSB)(fig.21)
22. Read the register 0x003 = 8’b1110_0000(Part ID-read only, should be 8’b1101_0011)(fig.22)
23. Read the 0x010 = 8’b0110_0100(Write data is 8’b0110_1110)(fig.23)
24. Read the register 0x014 = 8’b0000_0000(Write data is 8’b0000_1010, default value is 8’b0000_0011)(fig.24)
25. Read the register 0x016 = 8’b0000_0000(Write value is 8’b0000_0111, default value is 8’b000_0110)(fig.25)
26. Read the register 0x017 = 8’b0000_0000(Write value is 8’b1100_0100, default value is 8’b0000_0000)(fig.26)
27. Read the register 0x01C = 8’b0000_0000(Write value is 8’b0000_0111, default value is 8’b0000_0000)(fig.27)

 

Should I write all the registers in AD9517-4? Or the steps were wrong?

Actually, I have read the data from SDO some times, which means the registers were written correctly, but this time I failed again. 

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