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Unable to build FMCDAQ2 HDL files

Question asked by justinklchan on Jul 21, 2017
Latest reply on Jul 21, 2017 by justinklchan

I'm trying to build the HDL files for the FMCDAQ2 on the KC705 board here:

https://github.com/analogdevicesinc/hdl/tree/master/projects/daq2/kcu105 

 

When I make that directory I get these errors:

error copying "daq2_kc705.runs/impl_1/system_top.sysdef": no such file or directory
    while executing
"file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top.hdf"
    invoked from within
"if [expr [get_property SLACK [get_timing_paths]] < 0] {
    file copy -force $project_name.runs/impl_1/system_top.sysdef $project_name.sdk/system_top_..."
    (procedure "adi_project_run" line 26)
    invoked from within
"adi_project_run daq2_kc705"
    (file "system_project.tcl" line 14)
INFO: [Common 17-206] Exiting Vivado at Fri Jul 21 00:15:46 2017...

 

When I open up Vivado, this is what shows up in the error output:

[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted: i_system_wrapper/system_i/axi_ad9680_jesd/inst/i_system_axi_ad9680_jesd_0 (jesd204_v7_0_1_top__parameterized0) i_system_wrapper/system_i/axi_ad9144_jesd/inst/i_system_axi_ad9144_jesd_0 (jesd204_v7_0_1_top)   

 

I followed this help document:

https://www.xilinx.com/support/answers/58758.html 

But it made no change to the output. The errors were the same.

 

I have Vivado 2016.2 on a Linux machine. I have other versions including 2015.2 and 2017.2. My license for Vivado came with my KC705 eval board. I'm able to instantiate JESD related IP blocks without issue.

 

I'm aware a thread exists from a year ago with the same error. But the thread/error remained unresolved:

a problem of the reference HDL design for FMCDAQ2-EBZ with KC705 

So I'm hoping it will be solved here.

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