I'm trying to build the HDL files for the FMCDAQ2 on the KC705 board here:
When I make that directory I get these errors:
When I open up Vivado, this is what shows up in the error output:
[Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted: i_system_wrapper/system_i/axi_ad9680_jesd/inst/i_system_axi_ad9680_jesd_0 (jesd204_v7_0_1_top__parameterized0) i_system_wrapper/system_i/axi_ad9144_jesd/inst/i_system_axi_ad9144_jesd_0 (jesd204_v7_0_1_top)
I followed this help document:
But it made no change to the output. The errors were the same.
I have Vivado 2016.2 on a Linux machine. I have other versions including 2015.2 and 2017.2. My license for Vivado came with my KC705 eval board. I'm able to instantiate JESD related IP blocks without issue.
I'm aware a thread exists from a year ago with the same error. But the thread/error remained unresolved:
So I'm hoping it will be solved here.