I have a question about the AD9371 IP block as written by ADI.
For a standard implementation of the AD9371 chip, 4 JESD lanes are needed. Why are they organized in pairs for the 9371 reference design? In other words, why is there a separate lane pair producing 64 data bits for the adc_rx_data data port, and another 64 bits for adc_rx_os_data? Each one with its own 4 bits of start-of-frame (SOF).
What is the rationale of architecting this way, and what would be involved in converting this to run with a single 128-bit data bis and single 4-bit SOF bus?