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High speed ADC clocking and DDS Jitter

Question asked by YYHH on Oct 20, 2011
Latest reply on Oct 20, 2011 by DSB



I will use  AD9255 -105 14-bit ADC for a 36.15MHz IF sampled at 88MHz.

From ADC parameters and the IF I calculated that the sample clock should have less than 0.5 ps jitter.

I need the clock frequency to be finely tuned.

I was wondering if a DDS would be able to reach this low jitter level (AN823 seems to show that I would need a 1GHz sample rate). I would also need some general advice to choose a proper clock generator/clock architecture.