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Routing guidelines for 2xAD9361 with LVDS interface pls provide length matching and other details to be followed.

Question asked by ViR on Jul 20, 2017
Latest reply on Jul 28, 2017 by Vinod

We are using 2xAD9361 transceiver and after pre-routing, we achieved 5000 mils of trace length from FPGA to AD9361. 

Pls provide routing guidelines viz LVDS routing min and max spacing betn diff pairs and inter differential pairs.

From User manual, we have generated some data as below. 

 

Parameter

Description

min

Typ

Max

Length matching (inch)

tDDRx

Delay from DATA_CLK to Rx_D[5:0] outputs

0.25 ns

 

1.25 ns

1500mils to 7500mils

tDDDV

Delay from DATA_CLK to Rx_FRAME

0.25 ns

 

1.25 ns

1500mils to 7500mils

 

Note:6000 mils = 1000ps or 1ns for FR4

Please verify this and provide other details to finish the design.

Length matching and spacing..for RX/TX.FB_CLK/TX_FRAME/RX_FRAME/DATA_CLK....etc

 

Thanks & Regards

Vikrant

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