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Design and transmit dataformat for a 24bit/48kHz Signal

Question asked by Tschem on Oct 19, 2011
Latest reply on Jan 24, 2012 by DeepV



i'm trying to connect an external device to the ADSP-21489. this device (DAC AD5764R) has the standard serial interface (bclk, fsclk, data) and needs exact specifications for its format:


bitclocks work till 50kHz, fsync has to be exactly 24 bits wide. with the first falling edge of fsync the msb of the left channel-data has to be transmitted. after 24 cycles, exactly with the rising edge of fsync, the msb of the right channel has to be transmitted. so it's not exactly a l2s, nor a left-justified format. if data is too long or too short, the data on the DAC is invalid.


my questions:

-is the SPORT-interface useful for this? with pcg i've already managed to get a 24cycles wide sync-puls @ 48kHz, but the data-word is, independently from the SLEN setting, 32 bit wide (with zeroes at the end, if i'm correct). so the data on the external device is invalid. is there a possibility to let the SPORT just transmit 24 bits, without the zeroes?

-if the SPORT doesn't work, can i do this via SPI or something else??


thx in advace,