I want to decimate the output of the ADAR7251 ADC from 450 kSPS to 112.5 kSPS. This would be by a factor of 4. I plan on using 2 digital halfband filters on my FPGA.
Already the ADC oversamples by a factor of 48*Fs and thus relaxes the requirement for the anti-alias filter. FYI I'm using a 3rd order Bessel LPF (passband 60 kHz, stopband 180 kHz @ 20 dB of attenuation).
My question is can I do without the anti-alias halfband filters and simply take every 4th sample?