I use PPI interface of BF538 processor for coomunication with FPGA. 1 frame sync GP TX mode is used. PPI clock and FS1 are generated by FPGA. 12bit width words are generated by BF processor on rising edge of clock signal.The data length is 64. There are 8 extra clocks at the communication beginning. I have set the first and the second word to 0xFFF. The rest words are 0x000.
I have an following issue. When the delay register is set to 0, all data words are OK. But if the delay register is set to not zero value, the first data generated by BF are always 0x000.
Fig1 shows signal chart with delay register set to 0. You can see that both first and second MSB bit of Tx word is set to 1. It is OK.
But in the Fig2, where the delay register is set to 1, the first data is missing, the data pulse is only 1 clock period width. All other words are correct and delayed as expected. If I set e.g. last but one word to 0xFFF, it is on its expected position. It seems the PPI DMA is not able correcty drive PPI data pins if the delay register is set to non zero value.
The PPI clock frequency is about 1.5 MHz, SSCK frequency is set to about 115 MHz.
Here is part of my code in VDSP:
*pDMA0_PERIPHERAL_MAP = PMAP_PPI;
*pDMA0_START_ADDR = (void *)led_drv_cpld_video_buff; // buff of 16bits data
*pDMA0_X_MODIFY = 2;
*pDMA0_X_COUNT = LED_DRV_CPLD_VIDEO_BUFF_SIZE;
*pDMA0_CONFIG = FLOW_AUTO | DI_EN | WDSIZE_16 | DMAEN;
*pPPI_CONTROL = (1 << 14) | (3 << 11) | (3 << 2) | (1 << 1);
*pPPI_COUNT = LED_DRV_CPLD_VIDEO_BUFF_SIZE - 1;
*pPPI_DELAY = 1;
*pSIC_IMASK0 |= DMA0_IRQ;
*pSIC_IMASK0 |= DMAC0_ERR_IRQ;
*pPPI_CONTROL |= (1 << 0); // start
I feel hopeless, please help.