We've been experiencing an excessive rate of hung SDA lines with the ADXL345 digital accelerometer. These aren't always cleared via toggling SCL. I've got some related questions. What are the possible of effects of trying to communicate via I2C with an excessive rise time? I've measured a rise time (30-70%) of 536ns (almost doubling the max specified in the datasheet (300ns)). Also, our design does not seem to be connecting the VDDI/O pin per datasheet recommendations (its connected to 3V and Vs=2.5V). The Power Sequencing section of the datasheet states "VDDI/O can differ from Vs to accommodate the desired interface voltage, as long as Vs is greater than or equal to VDDI/O." What effects would be expected with this connection (and could one of them be I2C communication issues resulting in SDA being held low despite toggling SCL?)? Please also clarify the "communication bus conflict" issues related to VDDI/O being off (e.g., could a hung bus not responding to toggling SCL be one of them)?