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Questions regarding the AD9361 RFPLL-VCOs

Question asked by Schrank on Jul 14, 2017
Latest reply on Jul 14, 2017 by Vinod

Hello, I have some questions regarding the RFPLL-VCOs.


I would like to know if they are using multiple sub bands, using switched capacitors in parallel to the varactor, like the VCOs of chip in the link below for example.
http://www.st.com/content/ccc/resource/technical/document/datasheet/48/15/3b/e6/23/60/42/16/CD00166291.pdf/files/CD00166291.pdf/jcr:content/translations/en.CD00166291.pdf#page=23
We are concerned, if there is a possibility that the VCO toggles between two sub bands, each time it should lock to the same frequency, depending on temperature or other factors.


I also would like to ask, if the RFPLLs will stay locked over the whole rated operational temperature range of -40 to 85 °C or if an additional VCO calibration will be required.

In other words, when I save all the PLL parameters using a fastlock profile, will the profile be usable over the whole rated temperature range?

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