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FMCJESDADC1 KC705 SPI Reading FF

Question asked by SylviaF on Jul 13, 2017
Latest reply on Jul 19, 2017 by SylviaF

Hi!

 

I built the reference design for AD-FMCJESDADC1 FMC Board with Xilinx KC705 (https://wiki.analog.com/resources/fpga/xilinx/fmc/ad-fmcjesdadc1-ebz). It was successfully synthesized and implemented. Then I created a Xilinx SDK project as instructed (https://wiki.analog.com/resources/eval/user-guides/ad-fmcjesdadc1-ebz/software/baremetal).

 

I tested my KC705 with simple BIST test and it worked, so I loaded the board with reference design. When I tried to run Xilinx SDK project, I read "ff" on SPI for all part IDs and I couldn't read anything useful. I tried to add ILA to the reference design but it failed timing. I can't find more documentation about the reference design for further debugging.

 

I didn't edit anything in the reference design, so I'm not sure why it's not working.

 

SDK Terminal:

AD9517 PLL ok (0xFF).

AD9250 CHIP ID errors (0xFF).

AD9250 PLL/link errors (0x0).

AD9250 CHIP ID errors (0xFF).

AD9250 PLL/link errors (0x0).

JESD204B-GT-RX[3]: Invalid status, received(0x0FCFC), expected(0x000FF)!

JESD204B-GT-RX[2]: Invalid status, received(0x0FCFC), expected(0x000FF)!

JESD204B-GT-RX[1]: Invalid status, received(0x0FCFC), expected(0x000FF)!

JESD204B-GT-RX[0]: Invalid status, received(0x0FCFC), expected(0x000FF)!

JESD204B-GT-RX[3]: Invalid status, received(0x0FCFC), expected(0x1FFFF)!

JESD204B-GT-RX[2]: Invalid status, received(0x0FCFC), expected(0x1FFFF)!

JESD204B-GT-RX[1]: Invalid status, received(0x0FCFC), expected(0x1FFFF)!

JESD204B-GT-RX[0]: Invalid status, received(0x0FCFC), expected(0x1FFFF)!

JESD204B successfully initialized.

ADC Core Status errors.

ADC Core Status errors.

 

Thank you!

 

Sylvia

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