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Issues with PN sequence test mode

Question asked by Rekha on Jul 12, 2017
Latest reply on Jul 13, 2017 by UmeshJ

Hello All,

I'm using 9 bit PN sequence test mode pattern using AD9234. It's observed that data slip at the destination side (JESDRX204B, Kintex-7 FPGA) randomly . I make sure that ADC input clock is clean and there is no unusual behavior.

And also JESD PLL is locked (0x56F = 0x80) and input clock is detected (0x11C = 0x01). Please suggest what could be the source of this problem?