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Why is ADRV9371 Receive split into two halves?

Question asked by CodeWarrior on Jul 12, 2017
Latest reply on Jul 17, 2017 by mhennerich

Hi all,


I'm trying to understand why the ADRV9371 HDL design has a separate path for Rx and Rx_OS. Each of these receive paths has 2 JESD lanes, and a separate SYSREF. Is it possible to use a single 4-lane Receive block to do the interface in the FPGA, with a single SYSREF signal input?