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Conditions for TMDS PLL LOCK of ADV7511W

Question asked by Tamu on Jul 12, 2017
Latest reply on Aug 8, 2017 by Tamu



I have questions about the conditions for lock of the TMDS PLL of ADV7511W.


I think some conditions are required for lock of the PLL as follows:
1. Inputs (CLK, DE, VSYNC, HSYNC etc) for ADV7511 are stable.
2. Some following registers are set:
   0x15  (Input ID)
   0x16  (Output Format, Color Depth, Input Style, DDR Input Edge etc.)
   0x30 - 0x3A  (Hsync Placement/Duration, Vsync Placement/Duration, Hsync Delay, Vsync Delay,

                         Interlace Offset, Active Width, Active Height, etc.)


Is this correct?
If something is wrong, please let me know.
Also, if other conditions or registers are needed for the PLL lock, could you tell me the conditions?


Thank you!
Best regards.