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JESD204B Verilog Design

Question asked by Lt.Coder on Jul 11, 2017
Latest reply on Jul 20, 2017 by TonyM


   I'm interested with JESD204B FPGA design. "AD9250_EVALDZ" has been downloaded on ADI's pub ftp.

About the GTX, RXRECCLK will generate a "pclk" that should be 1/40 of the lane rate.

But I can not understand what the relationship between RXRECCLK and MGTREFCLK?