since you don't seem to answer my previos post of my former thread, I start a new one.
As I mentioned the PLL seems to work now, but what is really strange, is that the output power performance is far away from what it should be according to the datasheet.
For example: I generate a 48,5MHz output frequency at the output (open end, no termination--> because of debugging) and I measure almost -6dBm, but output power set to maximum in the VCO sub register Reg2. Please see the attached image:
when I switch to 100MHz or above, I get a completely reduced output, about -23dBm . Please see the attached image:
Why is the chip behaving like this? what can be the cause of such vast deviations? I programmed the chip according to your recommendations and with ADIsimPLL.