I've got a design with an ADCMP582, and the output oscillates whenever the differential input voltage gets under about 50mV. I saw the note in the datasheet about keeping the slew rate above 50V/us, but that can't be what's going on here; if you can't even get within 50mV of the threshold without it oscillating then any concept of a 4mV offset voltage would be preposterous.
The + side input comes from a 50R signal source, the - side from a slow DAC output through a 150R, 330nF lowpass filter. The RISE1 output is loaded with 50R to ground (offpage).
When the chip goes into oscillation, it does so at about 1.2 GHz, and seems to be kicking current back out through the + input; I can run down that trace with a FET probe and see the voltage waveform it's creating.
I tried adding some hysteresis, hence that 3k resistor which should be good for ~5mV. Hysteresis should fix the problem. Nada.