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IP core clocking in HDL Reference AD9361

Question asked by marcinsztajn on Jul 10, 2017
Latest reply on Sep 4, 2017 by marcinsztajn

Hi, 

I am using ZC706 and FMCOMMS3 board I am trying to understand clocking paths in reference design (2015_r2 release). My questions are:

1. Does l_clk signal has frequency equal sampling rate/4 (2T2R mode) and sampling frequency/2 (1T1R mode) ?

2. Does dac_upack is able to read (i.e. 64 bit interleaved data) and return (two pair I and Q samples) on the one clock cycle?

3. Is it a good way to delay dac_valid signal which says to DMA "send me data", and insert a modulation IP core between dac_upack and ad961 ? or there is another, better way to do some baseband processing ?

4. Which block and signal first send request for data from DMA in transmit path? 

Thanks in advance

Martin 

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