Dear to all,
I've to build a system with multiple ADC (3 or 6 quad ADC) and a single fpga. For each ADC i've a data clock at 500MHz and a frame clock. All the ADC are clocked with the same buffered clock at 125MHz ( with a proper length compensation).
Since the input clock for the ADCs is the same, is it possible to deserialize all the channels using just one data clock and frame clock coming from 1 ADC? ( Assuming also in this case a proper length compensation)
I'm a bit worried about some shift in the start of the frame clock between the ADCs.
Thanks in advance for you help and consideration.