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HMC7043 Sysref Timer Enable Question

Question asked by jnet on Jul 7, 2017
Latest reply on Jul 25, 2017 by kpeker

We are using HMC7043 devices in a cascaded structure (lead HMC7043 device followed by two other secondary HMC7043 devices in parallel with one another).  At startup, we align the divider phases.  We then initialize our other devices that are downstream from the secondary HMC7043 devices (ADC, DAC, SoC).  Next, we issue a pulsor request to the lead HMC7043.  This causes the secondary HMC7043 devices to issue a SYSREF pulse to the other devices.


After this process, we disable the SYSREF timer on the two secondary HMC7043 devices to minimize phase noise on our clock output channels.  If we wish to later issue the SYSREF pulse again, we enable the SYSREF timers on the secondary devices, and re-issue the pulsor request.


It appears that when we enable the SYSREF timers on the two secondary devices, a SYSREF pulse is generated by those devices.  After this, our desired SYSREF pulse occurs (the one caused by our pulsor request).  Is this expected behavior?


I have attached a scope capture which depicts this.