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My current design only requires the use of 2 TX and 2 RX JESD lanes. Can I leave the other JESD lanes unconnected and floating in my schematic?

Question asked by shalpin on Jul 5, 2017
Latest reply on Jul 6, 2017 by sripad

We've been trying to prototype this using the evaluation card and the Xilinx ZC706 board by simply turning off the unused links. This doesn't seem to work. Is this a valid way to use the AD9371 device?

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