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ADF4159 periodical locking problem

Question asked by tomislav.grubesa@geolux.hr on Jul 5, 2017
Latest reply on Jul 6, 2017 by tomislav.grubesa@geolux.hr

Hello All

 

We are having problem with locking of the ADF4159 + ADF5901. It seems that we can get lock got 75ms and after that CP voltage drops significantly for 25ms and lock is lost. In the PLL all ramping and FSK/PSK are disabled and we are just testing continuous wave output for the moment. On spectrum analyzer we can see frequency changes and all commands to PLL looks like working properly except this 75ms/25ms period of lock/no-lock.

 

In the attach are spectrogram of the signal and oscillograms of MUXOUT pin configured to lock-detect (yellow) and CP voltage after the filter on blue.

 

To setup PLL and VCO we are using Analog software to generate registers values and we just send this over SPI interface from our board. SPI signals, timing and delays between writes to registers are verified.

 

Recalibration of VCO doesn't affect operation and level change of AUX outputs also doesn't change operation. Div/2 and Div/4 for AUX output also doesn't have impact on the system operation. When changing from 12GHz to 6GHz feedback signals we have changed register values in PLL accordingly. 

 

Feedback line is direct differential controlled impedance line from VCO to PLL DC coupled on RO4350B material with effective length 9mm. Simulation performed on it with 0,2dB loss prediction. Same operation of PLL is recorded if we cut feedback line on the board and insert 0402 10pF capacitors to AUX and nAUX signals to AC couple the feedback.

 

Please provide some help, we are missing ideas now.

 

Thnx,

Tom

 

Lock-out & CP signals

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