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AD9269 Interleaved and FS test

Question asked by AngelaHwang Employee on Jul 4, 2017
Latest reply on Jul 5, 2017 by DougI

Hi HS ADC supporting team,


I am debugging customer system board designed with 5pcs of AD9269 withFPGA.

The symptom is that the output of ADC is not Full scale even in saturated environment or +FS test mode.

During debug, I found out that one bit or few bits are dropping about 0.6V out of 3V hight level condition, and FPGA detect is as Low and this bit is shown as missing. <refer to the attached scope shot>

My questions are

1) Which case can make this situation?  we tried to reduced FPGA voltage level from 3V into 2.5V, the result was quit improved but still few bits are missing in +FS test. The missing bits positions are changing.

2) In their schematics, they are using Interleaved mode - ADC_A/ADC_B output thru Single output channel. They turned off the other output channel by SPI command( Reg#05=x01, Reg#14=x30, Reg#FF=01).

Interesting point is that they physically connected Channel OutputA and OutputB together. Means trace pattern CHoutA_bit#15 connect to CHoutB_bit#15, CHoutA_bit#14 connect to CHoutB_bit#14,.....,CHoutA_bit#0 connect to CHoutB_bit#0.<refer to the attached schematics>. In this case, is there any possibility of reflection noise due to alternate side ADCoutput trace lines?

3) There are 4pins of  DRVDD in AD9269. What happens if disconnect 2pins of DRVDD in Pin#28/Pin#37? They are just influencing Channel A side by disconnecting or should be connected anycase?

4) What is the interchannel interference of this  device?


Best Regards,