I have been chasing down an intermittent problem (Host comms via SPI stops working) with our 21469 framework. It seems to be related to interrupts, but post-mortem debugging has not proved very fruitful so far.
What I did discover is that the illegal condition interrupt was disabled, but an illegal condition was being latched. After enabling the interrupt, I tracked down the illegal access to the following register save on the entry to an ISR written in ASM..
< from vector table... >
push sts; // save ASTAT and MODE1, apply MMASK to MODE1
jump link_port_rx_service (db);
px=r0; // save r0, move all 40 bits (extended floating-point precision!)
< in normal code space ...>
dm(save_dma8_r0) = px (lw); <<<< THIS INSTRUCTION WAS MISALIGNED
where save_dma8_r0 was an array of length 2, but wasn't aligned on a 64-bit boundary.
What I want to know, is what actually is the effect of this unaligned LW write? As I understand it, the 21469 is able to 'correct' for unaligned accesses when in SIMD normal word mode, but what about when using the LW modifier ? Could it get the odd / even addresses mixed up somehow ? As I say the problem is very intermittent & happens about once a day so I suspect there may some other interaction with DMA or something else which only happens now & again.
Since fixing the unaligned write, I haven't seen the original problem again, but it's only been about half a day, so may still happen...