I am using the HMC7044 evaluation board with the evaluation software, with the attached config file. I have attached a 122.8MHz clock to CLKIN0_P (and CLKIN0_N to GND).
After loading the settings file, PLL1 locks. PLL2 does not lock. I have to initialize an autotune trigger, otherwise PLL2 will not lock.
Initially, when I click "Slip", the divider will not slip. Only after I disable and re-enable the channel, the "slip" command functions normal.
Am I doing somethign wrong, or is this normal behaviour? Especially the cycle slipping not working surprises me, and maybe there is a better way to get the chip initialized properly?