I am using the AD9910 as a waveform generator in a FMCW application. The master reference clock in the system is a 1GHz crystal oscillator. The oscillator output is provided to the DDS chip as the source of clock signal. Also, the same signal is passed through a divide-by-4 divider and applied to the FPGA controlling the DDS as a 250MHz clock signal.
I am using the "no-dwell high" mode of the DDS digital ramp generator (DRG). The FPGA is sending a periodic rising edge to the DRCTL pin of the DDS. However, the sweeps do not seem to start periodically. Sometimes there is a 4ns (1 clock cycle) between successive sweep start points. I know that the internal changes occur at the rising edge of the SYNC_CLK signal which is also running at 250MHz. Since I am using the same 1GHz source for both the DDS and the FPGA, I believe that clocks are synchronous and I do not need to use the SYNC_CLK output of the DDS.
I wonder if the DDS always starts sweeps at the first rising edge of the internal SYNC_CLK after DRCTL is high or can that be occasionally at the second or third rising edge?
I will be so pleased with your reply.