I use an HMC7044 and try to generate 2.5 GHz. I have a 100 MHz VCXO in PLL1. This works fine. If I use the internal VCO in PLL2 I can generate the desired 2.5 GHz by setting register 0x0035 to 25.
However, I want to use an external VCO with a frequency range including 1.6 to 2.6 GHz in PLL2 and in this mode it seems like the LSB of register 0x0035 is ignored. If I set it to 25, I get 2.4 GHz (as if the register was set to 24) and if I set it to 23 I get 2.2 GHz (as if the register was set to 22). 24 also gives 2.4 GHz.
I have not found any mention of this behaviour in the data sheet. Is it true that odd feedback divider numbers are not supported with external VCOs in PLL2?
Register 0x0064 is set to 0 by the way.
A workaround is to divide the reference to PLL2 with 10 to get 50 MHz and set N2 to 50. This works, but I think it is worse for phase noise, which is very important in the application, so I would like to avoid it.