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AD9371 minimal design with Xilinx JESD core

Question asked by CodeWarrior on Jun 29, 2017
Latest reply on Jul 3, 2017 by CodeWarrior

Hello all,


I am transitioning a successful AD9361+Zynq+No-OS design to the AD9371+Zynq and have a question about the IP needed to get the AD9371 new chip working. Additionally, I've successfully built the ADRV9371 Vivado reference design for the ZC706. I also have a Xilinx JESD204B core license.


Is there an example of the AD9371 IP integrated with the Xilinx JESD core? The old AD9361 design ultimately required a single Vivado IP block to do all of the hardware control functions for the RF chip, where samples from the AD9361 could be directly streamed to FPGA fabric. Is there something similar that uses the axi_ad9371_core and Xilinx JESD to complete the datapath?


If not, what is the "minimum" of IP actually needed to configure the AD9371 by using the No-OS drivers and have it stream I/Q samples? DMA, IIO, etc. are all not needed...